In current complementary metal-oxide semiconductor (CMOS) scaling, the use of undoped FIN field-effect transistor (FET) devices is highly preferred as a device choice for CMOS at and beyond the 22 nanometer (nm) node. One key problem with undoped devices is the implementation of multiple threshold voltage (Vt) devices. One solution is to dope the FINFET device. To do so, however, for aggressively scaled devices has serious drawbacks from random dopant fluctuation (RDF) effects. One can also engineer gate stacks with different work functions for different Vt's. This however requires a substantial amount of process complexity.
Therefore, improved techniques for fabricating multiple Vt FINFET devices that avoid the above-described drawbacks would be desirable.